08-24-2025, 07:32 PM
Intel "Bartlett Lake-S" Steppings Suggest Third Rebrand of "Raptor Lake" as "Bartlet
"Bartlett Lake-S" is an interesting chip by Intel, given that its "Nova Lake-S" desktop processors with large L3 caches won't arrive before mid/late 2026. The chip is built on the idea that the "Raptor Cove" P-core offers gaming performance comparable or better to the "Lion Cove" P-cores implemented on "Arrow Lake-S." Intel figured that for a monolithic silicon with a similar die-size of "Raptor Lake-S," which has 8 P-cores and 4 E-core clusters, it could design a silicon with 12 P-cores for the same number of ring-stops, sharing the same 36 MB of L3 cache. A recent post on Twitter by Jaykihn highlights the stepping of this silicon as A0, but there's more to the story—apparently Intel will recycle its older "Raptor Lake" and "Alder Lake" silicon within "Bartlett Lake" generation, and refer to them as "Bartlett Lake Hybrid."
This "Bartlett Lake Hybrid" line of processors will reuse B0, C0, and H0 chips. The B0 chip is the original "Raptor Lake-S," which comes with an 8P+16E core-configuration, 36 MB of L3 cache, 2 MB of L2 cache per P-core, and 4 MB of L2 cache per E-core cluster. The C0 silicon is derived from "Alder Lake-S," with an 8P+8E config that has 1.25 MB of L2 cache per P-core and 2 MB of L2 cache per E-core cluster, with 30 MB of L3 cache. The H0 silicon originally drove the lower half of the 12th Gen Core family, it has 6 P-cores, each with 1.25 MB of L2 cache, no E-core clusters, and 18 MB of L3 cache. Read full story
https://www.techpowerup.com/340023/intel...ake-hybrid
"Bartlett Lake-S" is an interesting chip by Intel, given that its "Nova Lake-S" desktop processors with large L3 caches won't arrive before mid/late 2026. The chip is built on the idea that the "Raptor Cove" P-core offers gaming performance comparable or better to the "Lion Cove" P-cores implemented on "Arrow Lake-S." Intel figured that for a monolithic silicon with a similar die-size of "Raptor Lake-S," which has 8 P-cores and 4 E-core clusters, it could design a silicon with 12 P-cores for the same number of ring-stops, sharing the same 36 MB of L3 cache. A recent post on Twitter by Jaykihn highlights the stepping of this silicon as A0, but there's more to the story—apparently Intel will recycle its older "Raptor Lake" and "Alder Lake" silicon within "Bartlett Lake" generation, and refer to them as "Bartlett Lake Hybrid."
This "Bartlett Lake Hybrid" line of processors will reuse B0, C0, and H0 chips. The B0 chip is the original "Raptor Lake-S," which comes with an 8P+16E core-configuration, 36 MB of L3 cache, 2 MB of L2 cache per P-core, and 4 MB of L2 cache per E-core cluster. The C0 silicon is derived from "Alder Lake-S," with an 8P+8E config that has 1.25 MB of L2 cache per P-core and 2 MB of L2 cache per E-core cluster, with 30 MB of L3 cache. The H0 silicon originally drove the lower half of the 12th Gen Core family, it has 6 P-cores, each with 1.25 MB of L2 cache, no E-core clusters, and 18 MB of L3 cache. Read full story
https://www.techpowerup.com/340023/intel...ake-hybrid