06-10-2024, 11:52 AM
AMD "Strix Point" Die Annotated, Shows Zen 5 + Zen 5c Core Layout
AMD on Monday launched its Ryzen AI 300 line of mobile processors based on the 4 nm "Strix Point" monolithic silicon. This chip was described by AMD as having a maximum CPU core configuration of 12-core/24-thread, which would be a neat 50% increase in core-counts over the previous generation; but there's more to it. Although "Strix Point" implements "Zen 5," not all 12 CPU cores on the silicon are the regular variant of "Zen 5." The chip physically has four "Zen 5" cores, and eight "Zen 5c" compact cores. Nemez (GPUsAreMagic) attempted to annotate the "Strix Point" die based a high-resolution photo by System360Cheese from AMD's Computex keynote; and there are some interesting findings.
The annotation reveals that the four regular "Zen 5" cores, each with a 1 MB dedicated L2 cache, share a 16 MB L3 cache. The eight "Zen 5c" cores, on the other hand, appear to share a smaller 8 MB L3 cache, in what could be a separate CCX. They each have a 1 MB L2 cache, too. The "Zen 5c" cores have the same IPC as the "Zen 5" cores when measured with common INT and FP benchmarks that don't move a lot of data; however, it could lag behind in workloads with a lot of streaming data. What's more, the previous generation "Zen 4c" cores were traditionally limited to lower frequencies than regular "Zen 4" cores, as the physically compacted cores couldn't hold onto higher core voltages. If that's the case with "Zen 5c," then what we're really looking at with "Strix Point" is an interesting hybrid core setup with eight high-IPC efficiency cores.
https://www.techpowerup.com/323159/amd-s...ore-layout
AMD on Monday launched its Ryzen AI 300 line of mobile processors based on the 4 nm "Strix Point" monolithic silicon. This chip was described by AMD as having a maximum CPU core configuration of 12-core/24-thread, which would be a neat 50% increase in core-counts over the previous generation; but there's more to it. Although "Strix Point" implements "Zen 5," not all 12 CPU cores on the silicon are the regular variant of "Zen 5." The chip physically has four "Zen 5" cores, and eight "Zen 5c" compact cores. Nemez (GPUsAreMagic) attempted to annotate the "Strix Point" die based a high-resolution photo by System360Cheese from AMD's Computex keynote; and there are some interesting findings.
The annotation reveals that the four regular "Zen 5" cores, each with a 1 MB dedicated L2 cache, share a 16 MB L3 cache. The eight "Zen 5c" cores, on the other hand, appear to share a smaller 8 MB L3 cache, in what could be a separate CCX. They each have a 1 MB L2 cache, too. The "Zen 5c" cores have the same IPC as the "Zen 5" cores when measured with common INT and FP benchmarks that don't move a lot of data; however, it could lag behind in workloads with a lot of streaming data. What's more, the previous generation "Zen 4c" cores were traditionally limited to lower frequencies than regular "Zen 4" cores, as the physically compacted cores couldn't hold onto higher core voltages. If that's the case with "Zen 5c," then what we're really looking at with "Strix Point" is an interesting hybrid core setup with eight high-IPC efficiency cores.
https://www.techpowerup.com/323159/amd-s...ore-layout
